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esi esi 1 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. es29lv800d 8mbit(1m x 8/512k x 16) cmos 3.0 volt-only, boot sector flash memory general features ? single power supply operation - 2.7v -3.6v for read, program and erase operations ?sector structure - 16kbyte x 1, 8kbyte x 2, 32kbyte x 1 boot sectors - 64kbyte x 15sectors ? top or bottom boot block - es29lv800dt for top boot block device - es29lv800db for bottom boot block device ? package options - 48-pin tsop - 48-ball fbga ( 6 x 8 mm ) - pb-free packages - all pb-free products are rohs-compliant ? low vcc write inhibit ? manufactured on 0.18um process technology ? compatible with jedec standards - pinout and software compatible with single-power supply flash standard device performance ? read access time - 70ns / 90ns / 120ns ? program and erase time - program time : 6us/byte, 8us/word ( typical ) - sector erase time : 0.7sec/sector ( typical ) ? power consumption (typical values) - 200na in standby or automatic sleep mode - 7ma active read current at 5 mhz - 15ma active write current during program or erase ? minimum 100,000 program/erase cycles per sector ? 20 year data retention at 125 o c software features ? erase suspend / erase resume ? data# poll and toggle for program/erase status ? unlock bypass program ? autoselect mode ? auto-sleep mode after t acc + 30ns hardware features ? hardware reset input pin ( reset#) - provides a hardware reset to device - any internal device operation is terminated and the device returns to read mode by the reset ? ready/busy# output pin ( ry/by#) - provides a program or erase operational status about whether it is finished for read or still being progressed ? sector protection / unpr otection ( reset# , a9 ) - hardware method of locking a sector to prevent any program or erase operation within that sector - two methods are provided : - in-system method by reset# pin - a9 high-voltage method for prom programmers ? temporary sector un protection ( reset# ) - allows temporary un protection of previously protected sectors to change data in-system
esi esi 2 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. the es29lv800 is a 8 megabit, 3.0 volt-only flash memory device, organized as 1m x 8 bits (byte mode) or 512k x 16 bits (word mode) which is con- figurable by byte#. four boot sectors and fifteen main sectors are provided : 16kbytes x 1, 8kbytes x 2, 32kbytes x 1 and 64kby tes x 15. the device is manufactured with esi?s proprietary, high perfor- mance and highly reliable 0.18um cmos flash technology. the device can be programmed or erased in-system with standard 3.0 volt vcc supply ( 2.7v-3.6v) and can also be programmed in stan- dard eprom programmers. the device offers min- imum endurance of 100,000 program/erase cycles and more than 10 years of data retention. the es29lv800 offers access time as fast as 70ns or 90ns, allowing operation of high-speed micropro- cessors without wait states. three separate control pins are provided to eliminate bus contention : chip enable (ce#), write enable (we#) and output enable (oe#). all program and erase operation are automatically and internally performed and controlled by embed- ded program/erase algorithms built in the device. the device automatically generates and times the necessary high-voltage pulses to be applied to the cells, performs the verifi cation, and counts the num- ber of sequences. some status bits (dq7, dq6 and dq5) read by data# po lling or toggling between consecutive read cycles provide to the users the internal status of program/erase operation: whether it is successfully done or still being progressed. the es29lv800 is complete ly compatible with the jedec standard command set of single power sup- ply flash. commands are written to the internal command register using standard write timings of microprocessor and data can be read out from the cell array in the device with the same way as used in other eprom or flash devices. general product description
esi esi 3 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. product selector guide family part number es29lv800 voltage range 2.7 ~ 3.6v speed option 70 90 120 max access time (ns) 70 90 120 ce# access (ns) 70 90 120 oe# access (ns) 30 35 50 command register analog bias generator address latch byte# ce# oe# a<0:18> reset# vcc vss chip enable output enable logic vcc detector timer/ counter y-decoder x-decoder y-decoder cell array data latch/ sense amps input/output buffers sector switches dq0-dq15(a-1) ry/by# write state machine we # function block diagram
esi esi 4 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. pin description pin description a0-a18 19 addresses dq0-dq14 15 data inputs/outputs dq15/a-1 dq15 (data input/output, word mode) a-1 (lsb address input, byte mode) ce# chip enable oe# output enable we# write enable reset# hardware reset pin, active low byte# selects 8-bit or 16-bit mode ry/by# ready/busy output vcc 3.0 volt-only single power supply (see product selector guide for s peed options and voltage supply tolerances) vss device ground nc pin not connected internally logic symbol dq0 ~ dq15 (a-1) ry/by# byte# reset# oe# ce# a0 ~ a18 we# 19 16 or 8
esi esi 5 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. connection diagram 48-ball fbga (6 x 8 mm) (top view, balls facing down) a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# reset# nc nc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte# vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-pin standard tsop es29lv800 a13 a12 a14 a15 a16 dq15/ vss a9 we# oe# ce# a0 a1 a2 a4 nc a11 dq7 dq14 dq13 dq6 nc nc a18 dq5 nc a5 dq2 dq0 dq8 dq9 dq1 dq10 dq11 dq3 dq12 vcc dq4 a3 a10 a b c d e f g h 6 5 4 3 2 1 byte# a-1 a8 reset# ry/ a7 a17 a6 vss by#
esi esi 6 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. several device operational modes are provided in the es29lv800 device. commands are used to ini- tiate the device operations . they are latched and stored into internal registers with the address and data information needed to execute the device operation. the available device operational modes are listed in table 1 with the required inputs, controls, and the resulting outputs. each operational mode is described in further detail in the following subsec- tions. read the internal state of the device is set for the read mode and the device is ready for reading array data upon device power-up, or after a hardware reset. to read the stored data from the cell array of the device, ce# and oe# pins should be driven to v il while we# pin remains at v ih . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. word or byte mode of output data is determined by the byte# pin. no additional command is needed in this mode to obtain array data. standard micro- processor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device stays at the read mode until another operation is activated by writing commands into the internal command register. refer to the ac read cycle timing diagrams for further details ( fig. 16 ). word/byte mode configuration ( byte# ) the device data output can be configured by byte# into one of two modes : word and byte modes . if the byte# pin is set at logic ?1?, the device is configured in word mode, dq0 - dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is configured in byte mode, and only data i/o pins dq0 - dq7 are active and controlled by ce# and oe#. the data i/o pins dq8 - dq14 are tri- stated, and the dq15 pin is used as an input for the lsb (a-1) address. standby mode when the device is not se lected or activated in a system, it needs to stay at the standby mode, in which current consumption is greatly reduced with outputs in the high impedance state. device bus operations
esi esi 7 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. the device enters the cmos standby mode when ce# and reset# pins are both held at vcc + 0.3v. (note that this is a more restricted voltage range than v ih. ) if ce# and reset# are held at v ih , but not within vcc + 0.3v, the device will be still in the standby mode, but the standby current will be greater than the cmos standby current (0.2ua typi- cally). when the device is in the standby mode, only standard access time (t ce ) is required for read access, before it is ready for read data. and even if the device is deselected by ce# pin during erase or programming operation, the device draws active cur- rent until the operation is completely done. while the device stays in the standby mode, the output is placed in the high impedance state, independent of the oe# input. the device can enter the deep power-down mode where current consumption is greatly reduced down to less than 0.2ua typically by the following three ways: - cmos standby ( ce#, reset# = vcc + 0.3v ) - during the device reset ( reset# = vss + 0.3v ) - in autosleep mode ( after t acc + 30ns ) refer to the cmos dc characteristics table 7 for further current specification. autosleep mode the device automatically enters a deep power-down mode called the autosleep mode when addresses remain stable for t acc +30ns. in this mode, current consumption is greatly reduced ( less than 0.2ua typical ), regardless of ce#, we# and oe# control signals. writing commands to write a command or command sequences to ini- tiate some operations such as program or erase, the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin deter- mines whether the device accepts program data in bytes or words. refer to ?byte# timings for write operations? in the fig. 19 for more information. unlock bypass mode to reduce more the programming time, an unlock- bypass mode is provided. once the device enters this mode, only two write cycles are required to ini- tiate the programming operation instead of four cycles in the normal program command sequences which are composed of two unlock cycles, program set-up cycle and the last cycle with the program data and addresses. in this mode, two unlock cycles are saved ( or bypassed ). sector addresses the entire memory space of cell array is divided into a many of small sectors: 16kbytes x 1, 8kbytes x 2, 32kbytes x 1 and 64kbytes x 15 main sectors. in erase operation, a single se ctor, multiple sectors, or the entire device (chip eras e) can be selected for erase. the address space t hat each sector occupies is shown in detail in the table 3-4. autoselect mode flash memories are intended for use in applications where the local cpu alters memory contents. in such applications, manufacturer and device identifi- cation (id) codes must be accessible while the device resides in the target system ( the so called ?in-system program?). on the other hand, signature codes have been typically accessed by raising a9 pin to a high voltage in prom programmers. how- ever, multiplexing high voltage onto address lines is not the generally desired system design practice. therefore, in the es29lv800 device an autoselect command is provided to allow the system to access the signature codes without any high voltage. the conventional a9 high-voltage method used in the prom programers for sig nature codes are still sup- ported in this device. if the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read some useful codes such as manufacturer and device id from the internal reg- isters on dq7 - dq0. standard read cycle timings apply in this mode. in the autoselect mode, the fol- lowing three informations can be accessed through either autoselect command method or a9 high-volt- age autoselect method. refer to the table 2. - manufacturer id - device id - sector protection verify hardware device reset ( reset# ) the reset# pin provides a hardware method of resetting the device to read array data. when the reset# pin is driven low for at least a period of t rp ,
esi esi 8 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. the device immediately te rminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once after the device is ready to accept another command sequence, to ensure data integrity. cmos standby during device reset current is reduced for the duration of the reset# pulse. when reset# is held at vss + 0.3v, the device draws the greatly reduced cmos standby current ( i cc4 ). if reset# is held at v il but not within vss + 0.3v, the standby curr ent will be greater. ry/by# and terminating operations if reset# is asserted dur ing a program or erase operation, the ry/by# pin remains a ?0? (busy) until the internal reset operation is completed, which requires a time of t ready (during embedded algo- rithms). the system can thus monitor ry/by# to determine whether the reset operation is completed. if reset# is asserted wh en a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo rithms). the system can read data after the reset# pin returns to v ih , which requires a time of t rh. reset# tied to the system reset the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot- up firmware from the flash memory.refer to the ac characteristics tables fo r reset# parameters and to fig. 17 for the timing diagram. sector protection the es29lv800 features hardware sector protec- tion. in the device, sector protection is performed on the sector previously defined in the table 3-4. once after a sector is protecte d, any program or erase operation is not allowed in the protected sector. the previously protected sector s must be unprotected by one of the unprotect methods provided here before changing data in those sectors. sector protection can be implemented via two methods. - in-system protection - a9 high-voltage protection to check whether the se ctor protection was suc- cessfully executed or not, another operation called ? protect verification ? needs to be performed after the protection operation on a sector. all protection and protect verifications provided in the device are summarized in detail at the table 1. in-system protection ?in-system protection?, the primary method, requires v id (11.5v~12.5v) on the reset# with a6=0, a1=1, and a0=0. this method can be imple- mented either in-system or via programming equip- ment. this method uses standard microprocessor bus cycle timing. refer to fig. 26 for timing diagram and fig. 2 for the protection algorithm. a9 high-voltage protection ?high-voltage protection?, the alternate method intended only for programming equipment, must force v id (11.5~12.5v) on address pin a9 and con- trol pin oe# with a6=0, a1=1 and a0=0. refer to fig. 28 for timing diagram and fig. 4 for the protec- tion algorithm. sector unprotection the previously protected sectors must be unpro- tected before modifying any data in the sectors. the sector unprotection al gorithm unprotects all sectors in parallel. all unprotected sectors must first be protected prior to the first sector unprotection write cycle to avoid any over-erase due to the intrin- sic erase characteristics of the protection cell. after the unprotection operation, all previously protected sectors will need to be i ndividually re-protected. standard microprocessor bus cycle timings are used in the unprotection and unprotect verification operations. three unprotect methods are provided in the es29lv800 device. all unprotection and unprotect verification cycles are summarized in detail at the table 1. - in-system unprotection - a9 high-voltage unprotection - temporary sector unprotection
esi esi 9 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. in-system unprotection ?in-system unprotection ?, the primary method, requires v id (11.5v~12.5v) on the reset# with a6=1, a1=1, and a0=0. this method can be imple- mented either in-system or via programming equip- ment. this method uses standard microprocessor bus cycle timing. refer to fi g. 26 for timing diagram and fig. 3 for the unprotection algorithm. a9 high-voltage unprotection ?high-voltage unprotection?, the alternate method intended only for programming equipment, must force v id (11.5~12.5v) on address pin a9 and con- trol pin oe# with a6=1, a1=1 and a0=0. refer to fig. 29 for timing diagram and fig. 5 for the unpro- tection algorithm. temporary sector unprotect this feature allows tempor ary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset# pin to v id (11.5v-12.5v). during this mode, formerly protected sectors can be pro- grammed or erased by selecting the sector addresses. once v id is removed fr om the reset# pin, all the previously protected sectors are pro- tected again. fig. 1 shows the algorithm, and fig. 25 shows the timing diagrams for this feature. hardware data protection the es29lv800 device provides some protection measures against accidental erasure or program- ming caused by spurious system level signals that may exist during power transition. during power-up, all internal registers and latches in the device are cleared and the device automatically resets to the read mode. in addition, with its internal state machine built-in the device, any alteration of the memory contents or any initiation of new operation- can only occur after successful completion of spe- cific command sequences. and several features are incorporated to prevent inadvertent write cycles resulting from vcc power-up and power-down transi- tion or system noise. low vcc write inhibit when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power-up and power-down. the command register and all internal program/ erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until vcc is greater than v lko . the system must provide proper signals to the control pins to prevent unin- tentional writes when vcc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe#=v il , ce#=v ih or we#=v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we#=ce#=v il and oe#=v ih during power up, the device does not accept any commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. notes: 1. all protected sectors are unprotected . 2. all previously protected sectors are protected once again. figure 1. temporary sector unprotect operation start reset# = v id (note 1) perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2)
esi esi 10 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. operation ce# oe# we# reset# addresses (note 1) dq0 ~ dq7 dq8~dq15 byte# = v ih byte# = v il read l l h h a in d out d out dq8~dq14 = high-z, dq15 = a-1 write l h l h a in (note 3) (note 3) standby vcc+ 0.3v xx vcc+ 0.3v x high-z high-z high-z output disable reset l h h h x high-z high-z x x x l x high-z high-z in-system sector protect (note 2) lh l v id sa,a6=l, a1=h,a0=l (note 3) x x sector unprotect (note 2) l h l v id sa,a6=h, a1=h,a0=l (note 3) x x temporary sector unprotect x x x v id a in (note 3) (note 3) high-z a9 high-volt- age method sector protect l v id l h sa,a9=v id , a6=l, a1=h,a0=l (note 3) (note 3) high-z sector unprotect l v id l h sa,a9=v id , a6=h, a1=h,a0=l table 1. es29lv800 device bus operations legend : l=logic low=v il , h=logic high=v ih , v id =11.5-12.5v, x=don?t care, sa=sector address, a in =address in, d in =data in, d out =data out notes : 1. addresses are a18:a0 in word mode (byte#=v ih ) , a18:a-1 in byte mode (byte#=v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector pro- tection and unprotection? section. 3. d in or d out as required by command sequence, data polling, or sector protection algorithm. description ce# oe# we# a18 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq8~dq15 dq7~dq0 byte# = v ih byte# = v il manufactureid:esi l l h xx v id xlxll x x4ah device id: es29lv800 llh x x v id x l x l h 22h x dah(t),5bh(b) sector protection verification llhsa x v id xlxhl x x 01h(protected) 00h(unprotected) legend : t= top boot block, b = bottom boot block, l=logic low=v il , h=logic high=v ih , sa=sector address, x = don?t care table 2. autoselect codes (a9 high-voltage method)
esi esi 11 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. table 3. top boot sector addresses (es29lv800dt) sector sector address a18~a12 sector size (kbytes/kwords) (x8) address range (x16) address range remark sa0 0000xxx 64/32 00000h~0ffffh 00000h~07fffh main sector sa1 0001xxx 64/32 10000h~1ffffh 08000h~0ffffh sa2 0010xxx 64/32 20000h~2ffffh 10000h~17fffh sa3 0011xxx 64/32 30000h~3ffffh 18000h~1ffffh sa4 0100xxx 64/32 40000h~4ffffh 20000h~27fffh sa5 0101xxx 64/32 50000h~5ffffh 28000h~2ffffh sa6 0110xxx 64/32 60000h~6ffffh 30000h~37fffh sa7 0111xxx 64/32 70000h~7ffffh 38000h~3ffffh sa8 1000xxx 64/32 80000h~8ffffh 40000h~47fffh sa9 1001xxx 64/32 90000h~9ffffh 48000h~4ffffh sa10 1010xxx 64/32 a0000h~affffh 50000h~57fffh sa11 1011xxx 64/32 b0000h~bffffh 58000h~5ffffh sa12 1100xxx 64/32 c0000h~cffffh 60000h~67fffh sa13 1101xxx 64/32 d0000h~dffffh 68000h~6ffffh sa14 1110xxx 64/32 e0000h~effffh 70000h~77fffh sa15 11110xx 32/16 f0000h~f7fffh 78000h~7bfffh boot sector sa16 1111100 8/4 f8000h~f9fffh 7c000h~7cfffh sa17 1111101 8/4 fa000h~fbfffh 7d000h~7dfffh sa18 111111x 16/8 fc000h~fffffh 7e000h~7ffffh note : the addresses range is a18:a-1 in byte mode (byte#=v il ) or a18:a0 in word mode (byte#=v ih ).
esi esi 12 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. table 4. bottom boot sector addresses (es29lv800db) sector sector address a18~a12 sector size (kbytes/kwords) (x8) address range (x16) address range remark sa0 000000x 16/8 00000h~03fffh 00000h~01fffh boot sector sa1 0000010 8/4 04000h~05fffh 02000h~02fffh sa2 0000011 8/4 06000h~07fffh 03000h~03fffh sa3 00001xx 32/16 08000h~0ffffh 04000h~07fffh sa4 0001xxx 64/32 10000h~1ffffh 08000h~0ffffh main sector sa5 0010xxx 64/32 20000h~2ffffh 10000h~17fffh sa6 0011xxx 64/32 30000h~3ffffh 18000h~1ffffh sa7 0100xxx 64/32 40000h~4ffffh 20000h~27fffh sa8 0101xxx 64/32 50000h~5ffffh 28000h~2ffffh sa9 0110xxx 64/32 60000h~6ffffh 30000h~37fffh sa10 0111xxx 64/32 70000h~7ffffh 38000h~3ffffh sa11 1000xxx 64/32 80000h~8ffffh 40000h~47fffh sa12 1001xxx 64/32 90000h~9ffffh 48000h~4ffffh sa13 1010xxx 64/32 a0000h~affffh 50000h~57fffh sa14 1011xxx 64/32 b0000h~bffffh 58000h~5ffffh sa15 1100xxx 64/32 c0000h~cffffh 60000h~67fffh sa16 1101xxx 64/32 d0000h~dffffh 68000h~6ffffh sa17 1110xxx 64/32 e0000h~effffh 70000h~77fffh sa18 1111xxx 64/32 f0000h~fffffh 78000h~7ffffh note : the addresses range is a18:a-1 in byte mode (byte#=v il ) or a18:a0 in word mode (byte#=v ih ).
esi esi 13 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. start reset# = v id set up sector address count = 1 wait 1us first write cycle = 60h? sector protect: write 60h to sec- tor address with a6 = 0, a1 = 1, a0 = 0 wait 150us verify sector protect: write 40h to sec- tor address with a6 = 0, a1 = 1, a0 = 0 data = 01h? protect another sector? remove v id from reset# write reset command sector protect complete temporary sector unprotect mode no count=25? increment count read from sec- tor address with a6 = 0, a1 = 1, a0 = 0 device failed no yes yes no no reset count = 1 yes figure 2. in-system sector protect algorithm yes start reset# = v id set up first sector address count = 1 wait 1us first write cycle = 60h? sector unpro- tect: write 60h to sec- tor address with a6 = 1, a1 = 1, wait 15ms verify sector unprotect: write 40h to sec- tor address with a6 = 1, a1 = 1, a0 = 0 data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete temporary sector unprotect mode no count =1000? increment count read from sec- tor address with a6 = 1, a1 = 1, a0 = 0 device failed no yes yes no no set up next sector address ye s ye s all sectors protected ? protect all sectors: the indicated por- tion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address no ye s figure 3. in-system sector unprotect algorithm in-system protection / unprotection method
esi esi 14 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. no yes yes no set a9=oe#=v id remove v id from a9 and write reset command sector protection complete set sector address a<18 :12> ce#, a6, a0=v il reset#, a1=v ih protect another sector ? read data data = 01h? ce#,oe#,a6,a0=v il reset#, a1 = v ih set we# = v il start count = 1 wait 150 us set we# = v ih increase count count= 25? device failed yes no no yes yes no set a9=oe#=v id remove v id from a9 and write reset command sector unprotection complete set sector addressa<18 :12> read data set we# = v il count = 1 set we# = v ih start note: all sectors must be previously protected. wait 15ms ce#,oe#, a0=v il reset#, a6, a1=v ih data = 00h? the last sector address ? yes no increase sector address increase count device failed count=1000? ce#, a0=v il , reset#, a6, a1=v ih figure 5. sector un-protection algorithm (a9 high-voltage method) figure 4. sector protection algorithm (a9 high-voltage method) a9 high-voltage method
esi esi 15 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. writing specific address and data commands or sequences into the command register initiates device operations. table 5 defines the valid register command sequences. note that writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is required to return the device to normal operation. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever hap- pens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend com- mand, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands sectio n for more information. the system must issue t he reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next sectio n, reset command, for more information. see also requirements for reading array data in the device bus operations section for more informa- tion.the read-only operati ons table provides the read parameters, and fig. 16 shows the timing dia- gram reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to which the system was writ ing to the read mode. once erasure begins, how ever, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to which the system was writing to the read mode. if the program command sequence is written to a sec- tor that is in the erase suspend mode, writing the reset command returns the device to the erase-sus- pend-read mode. once programming begins, how- ever, the device ignore s reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend- read mode. if dq5 goes high during a program or erase opera- tion, writing the reset comm and returns the device to the read mode (or erase-suspend-read mode if the device was in erase-suspend). command definitions
esi esi 16 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. table 5. es29lv800 command definitions command definitions command sequence (note 1) cycles bus cycles (notes 2~5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 555 90 x00 4a byte aaa 555 aaa device id (top) word 4 555 aa 2aa 55 555 90 x01 da byte aaa 555 aaa x02 device id (bottom) word 4 555 aa 2aa 55 555 90 x01 5b byte aaa 555 aaa x02 sector protect verify (note 9) word 4 555 aa 2aa 55 555 90 (sa)x02 00/01 byte aaa 555 aaa (sa)x04 program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 12) 1 xxx b0 erase resume (note 13) 1 xxx 30 legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pul se, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a18-a12 uniquely select any sector. 9. the data is 00h for an unprotected sector and 01h for a protected sector. 10. the unlock bypass command is required prior to the unlock- bypass program command. 11. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 12. the system may read and progr am in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 13. the erase resume command is valid only during the erase suspend mode. notes: 1. see table 1 for descr iption of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15-dq8 are don ?t care in command sequences, except for rd and pd 5. unless otherwise noted, address bits a18-a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is requi red to return to the read mode (or to the erase-suspend-r ead mode if previously in erase suspend) when a device is in the autoselect mode, or if dq5 goes high (while the device is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15-dq8 are don?t care. see the autoselect command sequence section for more information.
esi esi 17 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. autoselect command the autoselect command se quence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected, including information about factory- locked or customer lockable version. table 5 shows the address and data requirements. this method is an alternative to ?a9 high-voltage method? shown in table 2, which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an address within sector that is either in the read mode or erase-suspend-read mode. the auto-select command may not be written while the device is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect com- mand sequence. once after the device enters the auto-select mode, the manufacture id code ( 4ah ) can be accessed by one of two ways. just one read cycle ( with a6, a1 and a0 = 0 ) can be used. or four consecutive read cycles ( with a6 = 1 and a1, a0 = 0 ) for con- tinuation codes (7fh) and then another last cycle for the code (4ah) (with a6, a1 and a0 = 0) can be used for reading the manufacturer code. - 4ah (one-cycle read) - 7fh 7fh 7fh 7fh 4ah (five-cycle read) the system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in erase suspend). identifier code address data manufacturer id 00h 4ah device id 01h dah(t), 5bh(b) sector protect verify (sa)02h 00 / 01 byte / word program the system may program the device by word or byte, depending on the state of the byte# pin . programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device auto- matically provides internally generated program pulses and verifies the programmed cell margin. table 5 shows the address and data requirements for the byte program command sequence. note that the autoselect is unavailable while a programming operation is in progress. start verify data ? increment address write program com- mand sequence data poll from system last address? yes programming completed embedded program algorithm in progress no no ye s note: see table 5 for program command sequence figure 6. program operation
esi esi 18 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. program status bits : dq7, dq6 or ry/by# when the embedded program algorithm is com- plete, the device then retu rns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. refer to the write operation status section table 6 for information on these status bits. any commands ignored during program- ming operation any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset can immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the re ad mode, to ensure data integrity. programming from ?0? back to ?1? programming is allowed in any sequence and across sector boundaries. but a bit cannot be pro- grammed from ?0? back to a ?1?. attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1? unlock bypass in the es29lv800 device, an unlock bypass pro- gram mode is provided for faster programming oper- ation. in this mode, two cycles of program command sequences can be saved. to enter this mode, an unlock bypass enter command should be first written to the system. the unlock bypass enter command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle contain- ing the unlock bypass command, 20h. the device then enters the unlock-bypass program mode. a two-cycle unlock bypass program command sequence is all that is r equired to program in this mode. the first cycle in this sequence contains the unlock bypass program set-up command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in th e standard program com- mand sequence, resulting in faster total program- ming time. table 5 shows the requirements for the command sequence. during the unlock-bypass mode, only the unlock- bypass program and unlock-bypass reset com- mands are valid. to exit the unlock-bypass mode, the system must issue the two-cycle unlock-bypass reset command sequ ence. the first cycle must con- tain the data 90h. the second cycle need to only contain the data 00h. the device then returns to the read mode. - unlock bypass enter command - unlock bypass reset command - unlock bypass program command chip erase command to erase the entire memory, a chip erase command is used. this command is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up com- mand. two additional unlock write cycles are then followed by the chip eras e command, which in turn invokes the embedded erase algorithm. the chip erase command erases the entire memory includ- ing all other sectors except the protected sectors, but the internal erase operation is performed on a single sector base. embedded erase algorithm the device does not require the system to prepro- gram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to pro- vide any controls or timings during these opera- tions. table 5 shows the address and data requirements for the chip erase command sequence. note that the autoselect is unavailable while an erase operation is in progress erase status bits : dq7, dq6, dq2, or ry/ by# when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write opera- tion status section table 6 for information on these status bits. commands ignored during erase operation any command written during the chip erase opera- tion are ignored. however, note that a hardware
esi esi 19 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. reset immediately terminates the erase operation.if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data. to ensure data integrity. fig. 7 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section for parameters, and fig. 21 section for timing diagrams. sector erase command by using a sector erase command, a single sector or multiple sectors can be erased. the sector erase command is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 5 shows the address and data requirements for the sector erase command sequence. note that the autoselect is unavailable while an erase operation is in progress. embedded sector erase algorithm the device does not require the system to prepro- gram prior to erase. the embedded erase algorithm automatically programs and verifies the entire mem- ory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings these operations. sector erase time-out window and dq3 after the command sequence is written, a sector erase time-out of 50us occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the num- ber of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 us, otherwise the last address and com- mand may not be accepted, and erasure may begin. it is recommended that processor interrupts be dis- abled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3:sector erase timer.). the time-out begins from the rising edge of the final we# pulse in the command sequence. any command other than sector erase or erase sus- pend during the time-out period resets the device to the read mo de. the system mu st rewrite the command sequence and any additional addresses and commands. status bits : dq7,dq6,dq2, or ry/by# when the sector erase embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can re ad data from the non- erasing sector. the system can determine the sta- tus of the erase operation by reading dq7,dq6,dq2, or ry/by# in the erasing sector. refer to the write operation status section table 6 for information on these status bits. valid command during sector erase once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hard- ware reset immediately terminates the erase oper- ation. if that occurs, the sector erase command start no no yes write erase command sequence (notes 1,2) data poll to erasing bank from system data = ffh? erasure completed embedded erase algorithm in progress notes: 1. see table 5 for erase command sequence 2. see the section on dq3 for infor mation on the sector erase timer figure 7. erase operation
esi esi 20 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. sequence should be reinitiated once the device has returned to reading array data, to ensure data integ- rity. fig. 7 illustrates the algo rithm for the erase opera- tion. refer to the erase and program operations tables in the ac characteristics section for parame- ters, and fig. 21 section for timing diagrams. erase suspend/ erase resume an erase operation is a long-time operation so that two useful commands are provided in the es29lv800 device erase suspend and erase resume commands. through the two commands, erase operation can be suspended for a while and the suspended operation can be resumed later when it is required. while the erase is suspended, read or program operations can be performed by the system. erase suspend command, (b0h) the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only dur- ing the sector erase operation, including the 50us time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embed- ded program algorithm. when the erase suspend command is written during the sector erase opera- tion, the device requires a maximum of 20us to sus- pend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time- out period and suspends the erase operation. read and program during erase-suspend- read mode after the erase operation has been suspended, the device enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for er asure. (the device ?erase suspends? all sectors se lected for erasure.) reading at any address within erase-suspended sec- tors produces status information on dq7-dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is ac tively erasing or is erase- suspended. refer to the write operation status sec- tion for information on these status bits (table 6). after an erase-suspended program operation is complete, the device returns to the erase-suspend- read mode. the system can determine the status for the program operation using the dq7 or dq6 status bits, just as in the standard byte program operation. refer to the write operation status section for more information. autoselect during erase-suspend- read mode in the erase-suspend-read mode, the system can also issue the autoselected command sequence. refer to the auto select mode and autoselect com- mand sequence section for details (table 5). erase resume command to resume the sector er ase operation, the system must write the erase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing.
esi esi 21 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. program unlock bypass auto- select read chip erase sector erase erase- suspend read pa/pd a0 20 90 00 f0 resume 30 b0 suspend 50us sa/30 sa/30 10 55 aa 80 55 aa done 90 command diagram figure 8. command diagram done done
esi esi 22 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. in the es29lv800 device, several bits are provided to determine the status of a program or erase oper- ation: dq2, dq3, dq5, dq6, dq7 and ry/by#. table 6 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/ by#, to determine whether an embedded program or erase operation is in progress or has been com- pleted. dq7 (data# polling) the data# polling bit, dq7, indicates to the host system whether an embedde d program or erase algorithm is in progress or completed, or whether a device is in erase sus pend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during programming during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is com- plete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector , data# polling on dq7 is active for approximately 250ns , then the device returns to the read mode. during erase during the embedded erase algorithm, data# poll- ing produces a ?0? on dq7 . when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors se lected for erasure to read valid status information on dq7. erase on the protected sectors after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is acti ve for approximately 1.8us , then the device returns to the read mode. if not all selected sectors are prot ected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. how- ever, if the system reads dq7 at an address within a protected sector, the status may not be valid. data# polling algorithm just prior to the completion of an embedded program or ease operation, dq7 may change asynchronously with dq0-dq6 while output enable(oe#) is asserted low. that is, this device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq0-dq7 will appear on successive read cycles. table 6 shows the outputs for data# polling on dq7. fig. 9 shows the data# pollin g algorithm. fig. 22 in the ac characteristics section shows the data# polling timing diagram. write operation status
esi esi 23 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. ry/by# ( ready/busy# ) the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open- drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to vcc. if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. table 6 shows the outputs for ry/by#. dq6 ( toggle bit i ) toggle bit i on dq6 indicates whether an embed- ded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence ( prior to the program or erase operation), and during the sec- tor erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops tog- gling. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively eras- ing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. how- ever, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7(see the sub- section on dq7:data# polling). dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 6 shows the outputs for toggle bit i on dq6. fig. 10 shows the toggle bi t algorithm. fig. 23 in the ?ac characteristics? section shows the toggle bit timing diagrams. fig. 24 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2 : (toggle bit ii). toggling on the protected sectors after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 1.8us , then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. if a program address falls within a protected sector, dq6 toggles for approximately 250ns after the program command sequence is writ- ten, then returns to reading array data. dq2 ( toggle bit ii ) the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively eras- ing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-sus- pended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence dq2 start no read dq7-dq0 addr = va dq7 = data ? no yes fail dq5 = 1 ? read dq7-dq0 addr = va dq7 = data ? yes pass yes no notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. duri ng chip erase, a valid address in any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5 figure 9. data# polling algorithm
esi esi 24 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. start no read dq7-dq0 toggle bit = toggle ? no yes program/erase operation not complete, write reset command dq5 = 1 ? read dq7-dq0 twice yes yes no read dq7-dq0 toggle bit = toggle ? program/erase operation complete note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1?. see the subsections on dq6 and dq2 for more information. toggles when the system reads at addresses within those sectors that have been selected for erasure . (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is acti vely erasing or is erase- suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot dist inguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 6 to compare outputs for dq2 and dq6. fig. 10 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsec- tion. fig. 23 shows the toggle bit timing diagram. fig. 24 shows how differently dq2 operates com- pared with dq6. reading toggle bits dq6/dq2 refer to fig. 10 for the following discussion. when- ever the system initially begins reading toggle bit status, it must read dq7-dq 0 at least twice in a row to determine whether a toggle bit is toggling. typi- cally, the system would note and store the value of the toggle bit after the fi rst read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7-dq0 on the following read cycle. however, if after the initial two r ead cycles, the system deter- mines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully com- pleted the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially deter- mines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. altern atively, it may choose to perform other system tasks. in this case, this sys- tem must start at the beginning of the algorithm when it returns to determine the status of the opera- tion (top of fig. 10). figure 10. toggle bit algorithm
esi esi 25 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. time-out also applies after each additional sector erase command. when the time-out period is com- plete, dq3 switches from a ?0? to a?1?. if the time between additional sector erase commands from the system can be assumed to be less than 50us , the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the com- mand sequence, and then read dq3. if dq3 is ?1?, the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erasure operation is complete. if dq3 is ?0?, the device will accept addi tional sector erase com- mands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. in table 6, dq3 status operation is well defined and summarized with other status bits, dq7, dq6, dq5, and dq2. dq5 ( exceeded timing limits ) dq5 indicates whether the program or erase time has exceeded a specified in ternal pulse count limit. under these conditions dq5 produces a ?1?, indi- cating that the program or erase cycle was not suc- cessfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0? only an erase operation can change a ?0? back to a ?1?. under this condition, the device halts the opera- tion, and when the timing limit has been exceeded, dq5 produces a ?1?. under both these conditions, the system must write th e reset command to return to the read mode. dq3 ( sector erase timer ) after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase time does not apply to the chip erase command.) if addi- tional sectors are selected for erasure, the entire table 6. write operation status notes : 1. dq5 switches to ?1? when an embedded program or embedded er ase operation has exceeded the maxi mum timing limits. refer to th e section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details . status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/ by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase sus- pend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
esi esi 26 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. 20ns 20ns +0.8v vss-0.5v vss-2.0v 20ns 20ns 20ns 20ns 2.0v vcc+0.5v vcc+2.0v negative overshoot positive overshoot absolute maximum ratings storage temperature plastic packages ..............................................-65 o c to +150 o c ambient temperature with power applied ...........................................-65 o c to +125 o c voltage with respect to ground vcc (note 1) ..........................................................-0.5v to +4.0v a9, oe# and reset# (note 2) ........................-0.5v to +12.5v all other pins (note 1) ...................................-0.5v to vcc + 0.5v output short ci rcuit current (note 3) ................. 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, input or i/o pins may overshoot vss to -2.0v for per- iods of up to 20ns. maximum dc voltage on input or i/o pins is vcc+0.5v. see fig. 11. during voltage transition, input or i/o pins may overshoot to vcc+2.0v for periods up to 20ns. see fig. 11. 2. minimum dc input voltage on pins a9, oe# and reset# is -0.5v . during voltage transitions, a9, oe# and reset# may overshoot vss to -2.0v for periods of up to 20ns. see fig. 11. maximum dc input voltage on pin a9 is +12.5v which may overshoot to +14.0v for periods up to 20ns. 3. no more than one output may be shorted to ground at a time. du- ration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions ab- ove those indicated in the operational sections of this datasheet is not implied. exposure of the device to absolute maximum rating con- ditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ).................................-40 o c to +85 o c commercial devices ambient temperature (t a )....................................0 o c to +70 o c vcc supply voltages vcc for all devices ............................................2.7v to 3.6v operating ranges define those limits between which the functio- nality of the device is guaranteed. figure 11. maximum overshoot waveform
esi esi 27 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. dc characteristics table 7. cmos compatible parameter symbol parameter description test conditions min typ max unit i li input load current v in =vss to vcc vcc=vcc max + 1.0 ua i lit a9 input load current vcc=vcc max; a9=12.5v 35 ua i lr reset# input load current vcc=vcc max; reset#=12.5v 35 ua i lo output leakage current vout=vss to vcc, vcc=vcc max + 1.0 ua i cci vcc active read current (notes 1,2) ce#=v il oe#=v ih , byte mode 5mhz 7 15 ma 1mhz 2 4 ce#=v il , oe#=v ih , word mode 5mhz 7 15 1mhz 2 4 i cc2 vcc active write current (note 2,3) ce#=v il , oe#=v ih , we#=v il 15 30 ma i cc3 vcc standby current (note 2) ce#, reset#= vcc+ 0.3v 0.2 10 ua i cc4 vcc reset current (note 2) reset#=vss + 0.3v 0.2 10 ua i cc5 automatic sleep mode (notes2,4) v ih = vcc + 0.3v v il = vss + 0.3v 0.2 10 ua v il input low voltage -0.5 0.5 v v ih input high voltage 0.7xvcc vcc+0.3 v v id voltage for autoselect and temporary sector unprotect vcc = 3.0v + 10% 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, vcc = vcc min 0.45 v v oh1 output high voltage i oh = -2.0ma, vcc = vcc min 0.85 vcc v v oh2 i oh = -100 ua, vcc = vcc min vcc - 0.4 v lko low vcc lock-out voltage (note 5) 2.3 2.5 v notes: 1. the icc current listed is typically less than 2 ma/mhz, with oe# at v ih , typical condition : 25 o c, vcc = 3v 2. maximum i cc specifications are tes ted with vcc = vcc max. 3. icc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mo de when addresses remain stable for t acc + 30ns. typical sleep mode current is 200 na. 5. not 100% tested.
esi esi 28 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. dc characteristics zero-power flash figure 12. i cc1 current vs. time (showing active and automatic sleep currents) 0 500 1000 1500 2000 2500 3000 3500 4000 5 10 15 time in ns supply current in ma icc1 (active read current) icc5 (automatic sleep mode) 12 10 8 6 4 2 0 1 2 3 45 frequency in mhz supply current in ma 2.7v 3.6v figure 13. typical i cc1 vs. frequency note : addresses are switching at 1 mhz note : t = 25 o c
esi esi 29 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. test condition 70 90 120 output load 1ttl gate output load capacitance, c l (including jig capacitance) 30 pf 100 pf 100 pf input rise and fall times 5 ns input pulse levels 0.0 - 3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v table 8. test specifications key to switching waveforms device under te s t 3.3v 2.7k c l ? 6.2k ? waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) figure 14. test setup note : diodes are in3064 or equivalent measurement level output input 3.0v 0.0v 1.5v 1.5v figure 15. input waveforms and measurement levels
esi esi 30 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. ac characteristics table 9. read-only operations parameter description test setup speed options unit jedec std. 70 90 120 t avav t rc read cycle time(note 1) min 70 90 120 ns t avqv t acc address to output delay ce#,oe#=v il max 70 90 120 ns t elqv t ce chip enable to output delay oe#=v il max 70 90 120 ns t glqv t oe output enable to output delay max 30 35 50 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns note : 1. not 100% tested a ddress oe# we# outputs t rc address stable high-z output valid ce# t oeh t oh t df reset# ry/by# 0v t acc t rh t rh t ce t oe figure 16. read operation timings high-z
esi esi 31 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. ce#,oe# reset# ry/by# 0v t ready t rp t rh ce#,oe# reset# ry/by# t ready t rp t rb figure 17. reset timings (b) during embedded algorithm (a) not during embedded algorithm ac characteristics table 10. hardware reset ( reset #) parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 us t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 us t rb ry/by# recovery time min 0 ns note : not 100% tested
esi esi 32 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. address input ce# byte# t fhqv dq15 output data output (dq0-dq7 ) data output (dq0-dq7) data output (dq0-dq14) address input dq15 output data output (dq0-dq14) t flqz t elfl t elfh oe# dq 15/a-1 byte# dq 0-dq14 dq 15/a-1 byte# switching switching from word to byte mode the falling edge of the last we# signal ce# byte# we# t set (t as ) t hold (t ah ) figure 19. byte# timing for write operations figure 18. byte# timing for read operations ac characteristics table 11. word/byte configuration (byte#) note : refer to the erase/program operations table for t as and t ah specifications. parameter description 70 90 120 unit jedec std. t elfl /t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 25 30 30 ns t fhqv byte# switching high to output active min 70 90 120 ns byte# switching switching from byte to word mode dq 0-dq14
esi esi 33 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. ac characteristics table 12. erase and program operations parameter description 70 90 120 unit jedec std. t avav t wc write cycle time (note 1) min 70 90 120 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 45 50 ns t aht address hold time from ce# or oe # high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 45 50 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 35 50 ns t whdl t wph write pulse width high min 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) byte typ 6 us word typ 8 t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec t vcs vcc setup time (note 1) min 50 us t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns notes: 1. not 100% tested. 2. see the ?erase and programming perfor mance? section for more information.
esi esi 34 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. notes : 1. pa = program address, pd = program data, dout is the true data at the program address. 2. illustration shows device in word mode. a ddress oe# we# data 555h ce# vcc ry/by# t wc program command sequence (last two cycles) pa pa pa t as t vcs t busy t whwh1 status dout a0h pd t wp t cs t wph t rb t ch read status data(last two cycles) t ds t dh figure 20. program operation timings ac characteristics t ah
esi esi 35 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. a ddress oe# we# data 2aah ce# vcc ry/by# t wc erase command sequence (last two cycles) va sa va t as t vcs t busy t whwh2 in progress complete 55h 30h t wp t cs t wph t rb t ch read status data 555h for chip erase 10h for chip erase t ds t dh notes : 1. sa = sector address(for se ctor erase), va = valid addre ss for reading status data(s ee ?write operation status?). 2. these waveforms are for the word mode. figure 21. chip/sector erase operation timings ac characteristics t ah
esi esi 36 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. a ddress oe# we# dq0-dq6 ce# ry/by# t rc figure 22. data# polling timings (during embedded algorithms) va va va t busy high-z valid data t ch t acc t ce t oh t df t oe t oeh true complement status data complement status data true valid data high-z dq7 note : va = valid address. illustration shows fi rst status cycle after command sequence, last status read cycle, and array data read c ycle ac characteristics
esi esi 37 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. a ddress oe# we# dq6/dq2 ce# ry/by# figure 23. toggle bit timings (during embedded algorithms) t oeph t dh t aht t aso t oeh valid status valid status valid status valid data valid data t ceph t aht t as t oe (first read) (second read) (stops toggling) note : va = valid address; not required for dq6. illustration shows fi rst two status cycle after command sequence, last status read cycle, and array data read cycle. dq6 we# enter embedded erasing dq2 enter suspend erase erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete figure 24. dq2 vs. dq6 note : dq2 toggles only when read at an address within an erase- suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. ac characteristics
esi esi 38 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. ce# reset# ry/by# t rsp figure 25. temporary sector unprotect timing diagram t vidr program or erase command sequence t vidr t rrb v id vss,v il , or v ih we# parameter description all speed options unit jedec std. t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 us t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 us ac characteristics table 13. temporar y sector unprotect note: not 100% tested.
esi esi 39 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. oe# we# ce# valid* 60h 40h sector protect : 150us, sector unprotect: 15ms v id figure 26. sector protect & unprotect timing diagram 60h valid* valid* status sector protect or unprotect v ih reset# 1us sa,a6, a1,a0 dq * for sector protect, a6=0,a1=1,a0=0 fo r sector unprotect, a6=1,a1=1,a0=0 ac characteristics verify
esi esi 40 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. ac characteristics table 14. alternate ce# controlle d erase and program operations parameter description 70 90 120 unit jedec std. t avav t wc write cycle time( note 1) min 70 90 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 45 50 ns t dveh t ds data setup time min 35 45 50 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 35 50 ns t elel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 6 us word typ 8 t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec notes : 1. not 100% tested 2. see the ?erase and programming perfor mance? section for more information.
esi esi 41 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. a ddress oe# we# reset# ce# ry/by# t wc figure 27. alternate ce# controlled write(erase/program) operation timings t busy dq7# t ah t as t wh t rh t whwh1 or 2 t ws t ghel a0 for program 55 for erase data d out pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pd for program sa for sector erase 555 for chip erase pa t cp t cph t ds t dh notes : 1. figure indicates last two bus cycl es of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data 3. dq7# is the complement of the data written to the device. dout is the data written to the device. 4. waveforms are for the word mode. ac characteristics data polling
esi esi 42 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. a<18:12> oe# we# reset# ce# vcc figure 28. sector protection timings (a9 high-voltage method) t wpp1 0x01 t st dq sax t oe say t oesp t csp t st t vidr t vidr a <0> a <1> a <6> a <9> v id v id table 15. ac characteristics parameter description value unit t oe output enable to output delay max 30/35/50 ns t vidr voltage transition time min 500 ns t wpp1 write pulse width for pr otection operation min 150 us t wpp2 write pulse width for unprotection operation min 15 ms t oesp oe# setup time to we# active min 4 us t csp ce# setup time to we# active min 4 us t vlht voltage transition time min 1 us t st voltage setup time min 4 us t vlht
esi esi 43 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. a<18:12> oe# we# reset# ce# vcc figure 29. sector unprotection timings (a9 high-voltage method) t wpp2 0x00 t st dq sa0 t oe sa1 t oesp t csp t st t vidr t vidr a <0> a <1> a <6> a <9> v id v id note : it is recommended to verify for all sectors. ac characteristics
esi esi 44 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 10 sec excludes 00h programming prior to erasure (note 4) chip erase time 14 sec byte program time 6 150 us exclude system level overhead (note 5) word program time 8 210 us chip program time (note 3) byte mode 6.3 18.9 sec word mode 4.2 12.6 notes: 1. typical program and erase times assume the following conditions: 25 o c, 3.0v vcc, 10,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 o c, vcc = 2.7v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip pr ogramming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algo rithm, all bytes are progr ammed to 00h before erasure. 5. system-level overhead is the time re quired to execute the two-or- four-bus-cycle sequence for the program command. see table 5 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 100,000 cycles . description min max input voltage with respect to vss on all pins exc ept i/o pins (including a9, oe#, and reset#) - 1.0v 12.5 v input voltage with respect to vss on all i/o pins - 1.0v vcc + 1.0 v vcc current - 100 ma +100 ma note: includes all pins except vcc. test conditions: vcc = 3.0 v, one pin at a time parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf fbga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf fbga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf fbga 3.9 4.7 pf table 17. latchup characteristics table 18. tsop, so, and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions ta = 25 o c, f=1.0mhz. parameter description test conditions min unit minimum pattern data retention time 150 o c 10 years 125 o c 20 years table 19. data retention table 16. erase and programming performance
esi esi 45 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. parallel to seating plane ? l r c 0.25mm (0.0098?) bsc b b a see detail a detail a -a- -b- see detail b d1 d n 2 ---- n 2 ---- 1 + a2 0.10 c e a1 -c- seating plane gauge plane -x- e/2 x = a or b b c1 b1 (c) with plating base metal detail b section b-b 0.08mm (0.0031?) m c a-b s 2 1 n e 5 4 5 9 67 7 package ts 48 jedec mo-142 (b) dd symbol min nom max a - - 1.20 a1 0.05 - 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 - 0.16 c 0.10 - 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 r 0.08 - 0.20 n48 0 5 3 notes: 1. controlling dimensions are in millimeters(mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark 4. to be determined at the seating plane. the seating plane is def- ined as the plane of contac t that is made when the package lea- ds are allowed to rest freely on a flat horizontal surface. 5. dimension d1 and e do not include mold protrusion. allowable mold protrusion is 0.15mm (0.0059?) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion sha ll be 0.08mm (0.0031?) total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07mm (0.0028?). 7. these dimensions apply to the flat section of the lead between 0.10mm (0.0039?) and 0.25mm (0.0098?) from the lead tip. 8. lead coplanarity shall be wi thin 0.10mm (0.004?) as measured from the seating plane. 9. dimension ? e ? is measured at the centerline of the leads. physical dimensions 48-pin standard tsop (m easured in millimeters)
esi esi 46 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. package xfbd 048 jedec n/a 6.00 mm x 8.00 mm package symbol min nom max note a 1.10 overall thick ness a1 0.21 0.25 0.29 ball height a2 0.7 0.76 0.82 body thickness d 8.00 bsc body size e 6.00 bsc body size d1 5.60 bsc ball footprint e1 4.00 bsc ball footprint md 8 row matrix sized direction me 6 row matrix sized direction n 48 total ball count b 0.30 0.35 0.40 ball diameter e 0.80 bsc ball pitch sd / se 0.40 bsc solder ball placement notes: 1. dimensioning and toleran cing per asme y14.5m-1994 2. all dimensions are in millimeters. 3. ball position designati on per jesd 95-1, spp-010. 4. e represents the sol der ball grid pitch. 5. symbol ? md ? is the ball row matrix size in the ? d ? direction. symbol ? me ? is the ball column matrix size in the ? e ? direct- ion. n is the maximum number of sol der balls for matrix si- ze md x me . 6. dimension ? b ? is measured at the maximum ball diameter in a plane parallel to datum z . 7. sd and se are measured with respect to datums a and b and define the position of the center solder ball in the out- er row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000 when there is an even number of solder balls in the outer row, sd or se = e /2 8. ? x ? in the package variations denotes part is outer qualifi- cation. 9. ? + ? in the package drawing in dicate the theoretical center of depopulated balls. 10. for package thickness a is the controlling dimension. 11. a1 corner to be indentified by chamfer, ink mark, metalli- zed markings indention or other means. 1 2 3 4 5 6 hfe g dcb a d a e a1 corner index mark 11 b d1 se 7 e1 pin 1 id. sd 7 6 a a1 10 a2 z 0.20 0.08 z 0.25 z (4x) // b 0.15 m z a b 0.08 m z e physical dimensions 48-ball fbga (6 x 8 mm)
esi esi 47 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. orderng information standard products esi standard products are available in several package and operating ranges. the order number (valid combi- nation) is formed by a combination of the following: temperature range blank : commercial (0 o c to + 70 o c) i : industrial (- 40 o c to + 85 o c) package type t : standard tsop (48-pin), w : fbga(48-ball) speed option 70 : 70ns 80 : 80ns 90 : 90ns 12 : 120ns sector architecture blank : uniform sector t : top sector b : bottom sector excel semiconductor component group 29 : flash memory technology d : 0.18um e : 0.15um f : 0.13um density & organization 400 : 4m ( x8 / x16) 800 : 8m ( x8 / x16) 160 : 16m ( x8 / x16) 320 : 32m ( x8 / x16) 640 : 64m ( x8 / x16) power supply and interface f : 5.0v lv : 3.0v dl : 3.0v, dual bank ds : 1.8v, dual bank bds : 1.8v, burst mode, dual bank es 29 lv 160 x x - xx x x x x pb-free c : pb product g : pb-free product voltage range blank : 2.7 ~ 3.6v r : 3.0 ~ 3.6v
esi esi 48 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. part no. es29lv800dt-70tgi es29lv800dt-70tci es29lv800db-70tgi es29lv800db-70tci es29lv800dt-90tgi es29lv800dt-90tci es29lv800db-90tgi es29lv800db-90tci es29lv800dt-12tgi es29lv800dt-12tci es29lv800db-12tgi es29lv800db-12tci es29lv800dt-70wgi es29lv800dt-70wci es29lv800db-70wgi es29lv800db-70wci es29lv800dt-90wgi es29lv800dt-90wci es29lv800db-90wgi es29lv800db-90wci es29lv800dt-12wgi es29lv800dt-12wci es29lv800db-12wgi es29lv800db-12wci speed 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns vcc 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v boot sector to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom package 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga pb pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - ball pitch/size 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm body size 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm product selection guide industrial device
esi esi 49 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. part no. es29lv800dt-70tg es29lv800dt-70tc es29lv800db-70tg es29lv800db-70tc es29lv800dt-90tg es29lv800dt-90tc es29lv800db-90tg es29lv800db-90tc es29lv800dt-12tg es29lv800dt-12tc es29lv800db-12tg es29lv800db-12tc es29lv800dt-70wg es29lv800dt-70wc es29lv800db-70wg es29lv800db-70wc es29lv800dt-90wg es29lv800dt-90wc es29lv800db-90wg es29lv800db-90wc es29lv800dt-12wg es29lv800dt-12wc es29lv800db-12wg es29lv800db-12wc speed 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 120ns 120ns 120ns 120ns vcc 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v boot sector to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom package 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga pb pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - ball pitch/size 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm body size 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm product selection guide commercial device
esi esi 50 rev. 1d january 5, 2006 es29lv800d excel semiconductor inc. excel semiconductor inc. 1010 keumkang hightech valley, sangdaewon1-dong 13 3-1, jungwon-gu, seongnam-si, kyongki-do, rep. of korea. zip code : 462-807 tel : +82-31-777-5060 fax : +82-31-740-3798 / homepage : www.excelsemi.com the attached datasheets are provided by excel semiconductor.inc (esi). esi reserves the right to change the spec- ifications and products. esi will answer to your qu estions about device. if you have any questions, please contact the esi office. document title 8m flash memory revision history revision number data items rev. 0a mar. 15, 2004 initial release version. rev. 0b apr. 23, 2004 1. the bias condtion of reset# in table 1 for a9 high-voltage method is changed from v id to h. 2. the bias condition of a9 in table 1 for a9 high-voltage method is added. 3. the typical byte and word program time are changed from 5us/7us to 6us/8us. 4. the dimension of fbga is changed from 8 x 9mm to 6 x 8mm. rev. 1a dec. 1, 2004 1. the preliminary is removed from the datasheet. 2. the 44 pin so is removed. 3. the icc3 (max) is changed from 5ua to 10ua. 4. the icc4 (max) is changed from 5ua to 10ua. 5. the icc5 (max) is changed from 5ua to 10ua. 6. the v il(max) is changed from 0.8v to 0.5v. 7. the overall thickness of fbga , a (max), is changed from 1.20 to 1.10. therefore, ball height (a1) and body thickness (a2) also is changed accordingly. 8. the ball diameter of fbga, b(min) , b(nom), b(max), is changed from 0.25, 0.30, and 0.35 to 0.30, 0.35, and 0.40 respectively. rev. 1b dec. 13, 2004 1. the arrow from erase suspend read to read is changed to sector erase. 2. v lko (min), 2.3v is added rev. 1c sep. 30, 2005 1. add tvlht parameter (page 42) rev. 1d jan. 5, 2006 1. add rohs-compliant package option

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